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june 2006 rev 2 1/52 52 l6730 L6730B adjustable step-down controller with synchronous rectification features input voltage range from 1.8v to 14v supply voltage range from 4.5v to 14v adjustable output voltage down to 0.6v with 0.8% accuracy over line voltage and temperature (0c~125c) fixed frequency voltage mode control t on lower than 100ns 0% to 100% duty cycle selectable 0.6v or 1.2v internal voltage reference external input voltage reference soft-start and inhibit high current embedded drivers predictive anti-crossconduction control selectable uvlo threshold (5v or 12v bus) programmable high-side and low-side r ds(on) sense over-current-protection switching frequency programmable from 100khz to 1mhz master/slave synchronization with 180 phase shift pre-bias start up capability (l6730) selectable source/sink or source only capability after soft-start (l6730) selectable constant current or hiccup mode overcurrent protection after soft-start (L6730B) power good output with programmable delay over voltage protection with selectable latched/not-latched mode thermal shut-down package: htssop20 applications high performance / high density dc-dc modules low voltage distributed dc-dc nipol converters ddr memory supply ddr memory bus termination supply htssop20 www.st.com order codes part number package packing l6730 htssop20 tube l6730tr htssop20 tape & reel L6730B htssop20 tube L6730Btr htssop20 tape & reel
contents l6730 - L6730B 2/52 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 pin connections and f unctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 internal ldo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3 bypassing the ldo to avoid the voltage drop with low vcc . . . . . . . . . . . . . 14 5.4 internal and external references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.5 error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.6 soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.7 driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.8 monitoring and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.9 adjustable masking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.10 multifunction pin (s/o/u l6730) (cc/o/u L6730B) . . . . . . . . . . . . . . . . . . . 27 5.11 synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.12 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.13 minimum on-time ton(min) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.14 bootstrap anti-discharging system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.14.1 fan power supply failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.14.2 no-sink at zero current operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
l6730 - L6730B contents 3/52 6 application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1 inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.2 output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.3 input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.4 compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.5 two quadrant or one quadrant operation mode (l6730) . . . . . . . . . . . . . . . . 36 7 l6730 demo board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.2 pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8 i/o description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9 efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10 pol demoboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
summary description l6730 - L6730B 4/52 1 summary description the controller is an integrated circuit ... designed using bicmos-dmos, v5 (bcd5) technology that provides complete control logic and protection for high performance, step-down dc/dc and nipol converters. it is designed to drive n-channel mosfets in a synchronous rectified buck converter topology. the output voltage of the converter can be precisely regulated down to 600mv, with a maximum tolerance of 0.8%, or to 1.2v, when one of the internal references is used. it is also possible to use an external reference from 0v to 2.5v. the input voltage can range from 1.8v to 14v, while the supply voltage can range from 4.5v to 14v. high peak current gate drivers provide for fast switching to the external power section and the output current can be in excess of 20a, depending on the number of the external mosfets used. the pwm duty cycle can range from 0% to 100% with a minimum on-time (t on(min) ) lower than 100ns, making conversions with a very low duty cycle and very high switching frequency possible. the device provides voltage-mode control. it in cludes a 400khz free-running oscillator that is adjustable from 100khz to 1mhz. the error amplifier features a 10mhz gain-bandwidth-product and 5v/s slew-rate that permits to realize high converter bandwidth for fast transient response. the device monitors the current by using the r ds(on) of both the high-side and low-side mosfet(s), eliminating the need for a current sensing resistor and guaranteeing an effective over current-protection in all the application conditions. when necessary, two different current limit protections can be externally set through tw o external resistors. a leading edge adjustable blanking time is also available to avoid false over-current-protection (ocp) intervention in every application condition. it is possible to select the hiccup mode or the constant current protection (L6730B) after the soft-start phase. during this phase constant current protection is provided. it is possible to select the sink-source or the sour ce-only mode capability (before the device powers on) by acting on a multifunction pin (l6730). the l6730 disables the sink mode capability during the soft-start in order to allow a proper start-up also in pre-biased output vo ltage conditions. the L6730B can always sink current and, so it can be used to supply the ddr memory bus termination. other features include master-slave synchronization (with 180 phase shift), power-good with adjustable delay, over voltage-protection, feed back disconnection, selectable uvlo threshold (5v and 12v bus), and thermal shutdown. the htssop20 package allows the realization for very compact dc/dc converters.
l6730 - L6730B summary description 5/52 1.1 functional description 1. in the L6730B the multifunction pin is: cc/ovp/uvlo. figure 1. block diagram l6730/b pgnd phase gnd lgate boot hgate och v in =1.8v to14v vo pgood fb ss/inh monitor protection and ref osc + - + - e/a pwm osc vccdr v cc =4.5v to14v + - 0.6v 1.2v ocl synch comp pgood tmask earef ldo masking time adjustment sink/ovp/uvlo*
electrical data l6730 - L6730B 6/52 2 electrical data 2.1 maximum rating table 1. absolute maximum ratings 2.2 thermal data table 2. thermal data symbol parameter value unit v cc v cc to gnd and pgnd, och, pgood -0.3 to 18 v v boot - v phase boot voltage 0 to 6 v v hgate - v phase 0 to v boot - v phase v v boot boot -0.3 to 24 v v phase phase -1 to 18 v phase spike, transient < 50ns (f sw = 500khz) -3 +24 ss, fb, earef, sync, osc, ocl, lgate, comp, s/o/ u, tmask, pgoodelay, v ccdr -0.3 to 6 v och pin maximum withstanding voltage range test condition: cdf-aec-q10 0-002 "human body model" acceptance criteria: "normal performance" 1500 v pgood pin 1000 other pins 2000 symbol description value unit r thja (1) 1. package mounted on demoboard max. thermal resistance junction to ambient 50 c/w t stg storage temperature range -40 to +150 c t j junction operating temperature range -40 to +125 c t a ambient operating temperature range -40 to +85 c
l6730 - L6730B pin connections and functions 7/52 3 pin connections and functions figure 2. pins connection (top view) 1. in the L6730B the multifunction pin is: cc/ovp/uvlo. table 3. pins connection pin n. name description 1 pgood delay a capacitor connected between this pin and gnd introduces a delay between the internal pgood comparator trigger and the external signal rising edge. no delay can be introduced on the falling edge of the pgood signal. the delay can be calculated with the following formula: 2 synch two or more devices can be synchronized by connecting the synch pins together. the device operating with the highest f sw will be the master device. the slave devices will operate at 180 phase shift from the master. the best way to synchronize devices is to set their f sw at the same value. if it is not used, the synch pin can be left floating. 3 sink/ovp/uvlo l6730 cc/ovp/uvlo L6730B with this pin it is possible: ? to enable-disable the sink mode current capability after ss (l6730); ? to enable-disable the constant current ocp after ss (L6730B); ? to enable-disable the latch mode for the ovp; ? to set the uvlo threshold for the 5v bus and 12v bus. the device captures the analog value pres ent at this pin at the start-up when v cc meets the uvlo threshold. 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 htssop20 10 17 18 19 20 osc ss/inh comp fb gnd synch pgood delay tmask earef pgood phase hgate boot vcc vccdr lgate ocl och pgnd 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 htssop20 10 17 18 19 20 osc ss/inh comp fb gnd synch pgood delay tmask earef pgood phase hgate boot vcc vccdr lgate ocl och pgnd sink/ovp/uvlo () pf c pgdelay ? = 5 . 0 [ s]
pin connections and functions l6730 - L6730B 8/52 4 t mask the user can select two different values for the leading edge blanking time on the peak overcurrent protection by connecting this pin to v ccdr or gnd. the device captures the analog value present at this pin at the start-up when v cc meets the uvlo threshold. 5 gnd all of the internal references are referenced to this pin. 6fb this pin is connected to the error amplif ier inverting input. connect it to vout through the compensation network. this pi n is also used to sense the output voltage in order to manage the over voltage conditions and the pgood signal. 7comp this pin is connected to the error amplifier output and used to compensate the voltage control loop. 8 ss/inh the soft-start time is programmed connecting an external capacitor from this pin and gnd. the internal current generator forces a current of 10 a through the capacitor. this pin is also used to inhibit the device: when the voltage at this pin is lower than 0.5v the device is disabled. 9 earef it is possible to set two internal references 0.6v / 1.2v or provide an external reference from 0v to 2.5v: ? v earef from 0% to 80% of v ccdr ? > external reference ? v earef from 80% to 95% of v ccdr ? > v ref =1.2v ? v earef from 95% to 100% of v ccdr ? > v ref =0.6v an internal clamp limits the maximum v earef at 2.5v (typ.). the device captures the analog value present at this pin at the start-up when v cc meets the uvlo threshold. 10 osc connecting an external resistor from this pin to gnd, the external frequency can be increased according with the following equation: connecting a resistor from this pin to v ccdr (5v), the switching frequency can be lowered according with the following equation: if the pin is left open, the switching frequency is 400 khz. normally this pin is at a voltage of 1.2v. in ovp the pin is pulled up to 4.5v (only in latched mode). don?t connect a capacitor from this pin to gnd. table 3. pins connection ) ( 10 88 . 9 400 6 ? ? + = k r khz fsw osc ) ( 10 01 . 3 400 7 ? ? ? = k r khz fsw osc
l6730 - L6730B pin connections and functions 9/52 11 ocl a resistor connected from this pin to ground sets the valley- current-limit. the valley current is sensed through the lo w-side mosfet(s). the internal current generator sources a current of 100 a (i ocl ) from this pin to ground through the external resistor (r ocl ). the over-current threshold is given by the following equation: connecting a capacitor from this pin to gnd helps in reducing the noise injected from v cc to the device, but can be a low impedance path for the high- frequency noise related to the gnd. connect a capacitor only to a ?clean? gnd. 12 och a resistor connected from this pin and the high-side mosfet(s) drain sets the peak-current-limit. the peak current is sensed through the high-side mosfet(s). the internal 100 a current generator (i och ) sinks a current from the drain through the external resistor (r och ). the over-current threshold is given by the following equation: 13 phase this pin is connected to the source of the high-side mosfet(s) and provides the return path for the high-side driver. this pin monitors the drop across both the upper and lower mosfet(s) for t he current limit together with och and ocl. 14 hgate this pin is connected to the high-side mosfet(s) gate. 15 boot the high-side driver is supplied through th is pin. connect a capacitor from this pin to the phase pin, and a diode from v ccdr to this pin (cathode versus boot). 16 pgnd this pin has to be connected closely to the low-side mosfet(s) source in order to reduce the noise injection into the device. 17 lgate this pin is connected to the low-side mosfet(s) gate. 18 v ccdr 5v internally regulated voltage. it is us ed to supply the internal drivers and as a voltage reference. filter it to gnd with at least a 1f ceramic cap. 19 v cc supply voltage pin. the operative supply voltage range is from 4.5v to 14v. 20 pgood this pin is an open collector output and it is pulled low if the output voltage is not within the specified thresholds (90%-110%). if not used it may be left floating. pull up this pin to v ccdr with a 10k resistor to obtain a logical signal. table 3. pins connection dsonls r 2 ocl r ocl i valley i ? ? = dsonhs r och r och i peak i ? =
l6730 - L6730B electrical characteristics 10/52 4 electrical characteristics v cc = 12v, t a = 25c unless otherwise specified table 4. electrical characteristics symbol parameter test condition min. typ. max. unit v cc supply current i cc v cc stand by current osc = open; ss to gnd 7 9 ma v cc quiescent current osc= open; hg = open, lg = open, ph=open 8.5 10 power-on 5v bus tu r n - o n v cc threshold v och = 1.7v 4.0 4.2 4.4 v tu r n - o f f v cc threshold v och = 1.7v 3.6 3.8 4.0 12v bus tu r n - o n v cc threshold v och = 1.7v 8.3 8.6 8.9 tu r n - o f f v cc threshold v och = 1.7v 7.4 7.7 8.0 v in ok tu r n - o n v och threshold 1.1 1.25 1.47 tu r n - o f f v och threshold 0.9 1.05 1.27 v ccdr regulation v ccdr voltage v cc =5.5v to 14v i dr = 1ma to 100ma 4.555.5v soft start and inhibit i ss soft start current ss = 2v 7 10 13 a ss = 0 to 0.5v 20 30 45 oscillator f osc initial accuracy osc = open 380 400 420 khz f osc,rt total accuracy rt = 390k ? to v ccdr rt = 18k ? to gnd -15 15 % ? v osc ramp amplitude 2.1 v output voltage (1.2v mode) v fb output voltage 1.190 1.2 1.208 v output voltage (0.6 mode) v fb output voltage 0.597 0.6 0.603 v
l6730 - L6730B electrical characteristics 11/52 symbol parameter test condition min. typ. max. unit error amplifier r earef earef input resistance vs. gnd 70 100 150 k ? i fb i.i. bias current v f = 0v 0.290 0.5 a ext ref clamp 2.3 v v offset error amplifier offset vref = 0.6v -5 +5 mv g v open loop voltage gain guaranteed by design 100 db gbwp gain-bandwidth product guaranteed by design 10 mhz sr slew-rate comp = 10pf guaranteed by design 5v/ s gate drivers r hgate_on high side source resistance v boot - v phase = 5v 1.7 ? r hgate_off high side sink resistance v boot - v phase = 5v 1.12 ? r lgate_on low side source resistance v ccdr = 5v 1.15 ? r lgate_off low side sink resistance v ccdr = 5v 0.6 ? protections i och och current source v och = 1.7v 90 100 110 ? i ocl ocl current source 90 100 110 ? ovp over voltage trip (v fb / v earef ) v fb rising v earef = 0.6v 120 % v fb falling v earef = 0.6v 117 % i osc osc sourcing current v fb > ovp trip v osc = 3v 30 ma power good upper threshold (v fb / v earef ) v fb rising 108 110 112 % lower threshold (v fb / v earef ) v fb falling 88 90 92 % v pgood pgood voltage low i pgood = -5ma 0.5 v table 4. electrical characteristics
electrical characteristics l6730 - L6730B 12/52 table 5. thermal characterizations (v cc = 12v) symbol parameter test condition min typ max unit oscillator f osc initial accuracy osc = open; t j =0c~ 125c 376 400 424 khz output voltage (1.2v mode) v fb output voltage t j = 0c~ 125c 1.188 1.2 1.212 v t j = -40c~ 125c 1.185 1.2 1.212 v output voltage (0.6v mode) v fb output voltage t j = 0c~ 125c 0.596 0.6 0.605 v t j = -40c~ 125c 0.593 0.6 0.605 v
l6730 - L6730B device description 13/52 5 device description 5.1 oscillator the switching frequency is inte rnally fixed to 400k hz. the internal osc illator generates the triangular waveform for the pwm charging and discharging an internal capacitor (f sw = 400khz). this current can be vari ed using an external resistor (r t ) connected between osc pin and gnd or v ccdr in order to change the switching frequency. since the osc pin is maintained at fixed voltage (typ. 1.2v), the frequ ency is increased (or decreased) proportionally to the current sunk (sourced) from (into) the pin. in particular by connecting r t versus gnd the frequency is increased (current is sunk from the pin), according to the following relationship: connecting r t to v ccdr reduces the frequency (current is sourced into the pin), according to the following relationship: switching frequency variation vs. r t is shown in figure 3. . figure 3. switching frequency variation versus rt. ) ( 10 88 . 9 400 6 ? ? + = k r khz fsw osc (1) ) ( 10 01 . 3 400 7 ? ? ? = k r khz fsw osc (2) switching frequency variation 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 0 100 200 300 400 500 600 700 800 900 1000 rosc (kohm ) fsw (khz) rosc connected to gnd rosc connected to vccdr
device description l6730 - L6730B 14/52 5.2 internal ldo an internal ldo supplies the internal circuitry of the device. the input of this stage is the v cc pin and the output (5v) is the v ccdr pin (see figure 4. ). 5.3 bypassing the ldo to avoid the voltage drop with low vcc the ldo can be by passed by providing 5v voltage directly to v ccdr . in this case vcc and v ccdr pins must be shorted together as shown in figure 5. v ccdr pin must be filtered with at least 1 f capacitor to sustain the internal ldo during the recharge of the bootstrap capacitor. v ccdr also represents a voltage reference for tmask pin, s/o/u pin (l6730) or cc/o/u pin (L6730B) and pgood pin (see table 3: pins connection ). if vcc 5v the internal ldo works in dropout with an output resistance of about 1 ? . the maximum ldo output current is about 100ma, and so the output voltage drop can be 100mv. the ldo can be bypassed to avoid this. figure 4. ldo block diagram. figure 5. bypassing the ldo ldo 4.5v 14v
l6730 - L6730B device description 15/52 5.4 internal and external references it is possible to set two internal references, 0.6v and 1.2v, or provide an external reference from 0v to 2.5v. the maximum value of the external reference depends on the v cc : with v cc = 4v the clamp operates at about 2v (typ.), while with v cc greater than 5v the maximum external reference is 2.5v (typ). v earef from 0% to 80% of v ccdr ? > external reference v earef from 80% to 95% of v ccdr ? > v ref = 1.2v v earef from 95% to 100% of v ccdr ? > v ref = 0.6v providing an external reference from 0v to 450mv the output voltage will be regulated but some restrictions must be considered: the minimum ovp threshold is set at 300mv. the under-voltage-protection doesn?t work. the pgood signal remains low. to set the resistor divider it must be considered that a 100k pull-down resistor is integrated into the device (see figure 6. ). finally it must be taken into account that the voltage at the earef pin is captured by the device at the start-up when vcc is about 4v. 5.5 error amplifier figure 6. error amplifier reference 2.5 v 100k earef v ccdr 0.6 v 1.2 v ext error amplifier ref.
device description l6730 - L6730B 16/52 5.6 soft-start when both v cc and v in are above their turn-on thresholds (v in is monitored by the och pin) the start-up phase takes place. otherwise the ss pin is internally shorted to gnd. at start-up, a ramp is generated charging the external capacitor c ss with an internal current generator. the initial value for this current is 35a and charges the capacitor up to 0.5v. after that it becomes 10a until the final charge value of approximately 4v (see figure 5. ). figure 7. device start-up: voltage at the ss pin. t t 0.5v 4v v cc v in v ss 4.2v 1.25v 4.2v or 8.6v 0.5v vcc vin 0.5v 1.25v vss 4v
l6730 - L6730B device description 17/52 the output of the error amplifier is clamped with this voltage (vss) until it reaches the programmed value. no switching activity is observable if v ss is lower than 0.5v and both mosfets are off. when vss is between 0.5v and 1.1v the low-side mosfet is turned on because the output of the error amplifier is lower than the valley of the triangular wave and so the duty-cycle is 0%. as v ss reaches 1.1v (i.e. the oscillator tr iangular wave infe rior limit) even the high-side mosfet begins to switch and the output voltage starts to increase. the l6730 - L6730B can only source current during the soft-start phase in order to manage the prebias start-up applications. this means that when the startup occurs with output voltage greater than 0v (pre-bias startup), even when vss is between 0.5v and 1.1v the low-side mosfet is kept off (see figure 8. and figure 9. ). figure 8. start-up without prebias figure 9. start-up with prebias lgate v out i l v ss v ss i l v out lgate
device description l6730 - L6730B 18/52 the L6730B can always sink current and so it can be used to supply the ddr memory termination bus. if overcurrent is detected during the soft-start phase, the device provides constant current-protection. in case there is short soft-start time and/or small inductor value and/or high output capacitors value and thus, in case of high ripple current during the soft-start, the converter can start-up in anyway and limit the current ( chapter 5.8: monitoring and protection on page 21 ) but not enter into hiccup mode. the soft-start phase ends when v ss reaches 3.5v. after that the over current-prote ction triggers the hiccup mode (l6730). with the L6730B there is the possibilit y to set the hiccup mode or the constant current mode after the soft-start acting on the multifunction pin cc/ o/u. with the l6730 the low-side mosfet(s) management after soft-start phase depends on the s/o/u pin state (see related section). if the sink mode is enabled the converter can sink current after soft-start (see figure 10. ) while, if the sink mode is disabled the converter never sinks current (see figure 11. ). figure 10. sink mode enabled: inductor current during and after soft-start (l6730). v out i l v ss v cc
l6730 - L6730B device description 19/52 during normal operation, if any under voltage is detected on one of the two supplies (v cc , v in ), the ss pin is internally shorte d to gnd by an intern al switch so the ss capacitor is rapidly discharged. two different turn-on uvlo thresholds can be set: 4.2v for 5v bus and 8.6v for 12v bus. figure 11. sink mode disabled: inductor current during and after soft-start (l6730). vout vss vcc i l
device description l6730 - L6730B 20/52 5.7 driver section the high-side and low-side drivers allow for the use of different types of power mosfets (also multiple mosfets to reduce the r dson ), maintaining fast switchi ng transitions. the low-side driver is supplied by v ccdr while the high-side driver is supplied by the boot pin. a predictive dead time control avoids mosfets cross-conduction maintaining very short dead time duration (see figure 12. ). the control monitors the phase node in order to sense the low-side body diode recirculation. if the phase node voltage is less than a certain threshold (?350mv typ.) during the dead time, it will be reduced in the next pwm cy cle. the predictive dead time control does not work when the high-side body diode is conducting beca use the phase node does not go negative. this situation happens when the converter is sinking current for example and, in this case, an adaptive dead time control operates. figure 12. dead times
l6730 - L6730B device description 21/52 5.8 monitoring and protection the output voltage is monitored by the fb pin. if it is not within 10% (typ.) of the programmed value, the power-good (pgood) output is forced low. the pgood signal can be delayed by adding an external capacitor on pgdelay pin (see table 3: pins connection and figure 13. ); this can be useful to perform cascade sequenc ing. the delay can be calculated with the following formula: the device provides over voltage protection: when the voltage sensed on fb pin reaches a value 20% (typ) greater than the reference, the low-side driver is turned on. if the ovp not- latched mode has been set the low-side mosfet is kept on as long as the overvoltage is detected (see figure 14. ).the ovp latched-mode has been set the low-side mosfet is turned on until v cc is toggled (see figure 15. ). in case of latched-mode ovp the osc pin is forced high (4.5v typ) if an over voltage is detected. figure 13. pgood signal () pf c pgdelay ? = 5 . 0 2ms/div. pgood fb
device description l6730 - L6730B 22/52 figure 14. ovp not latched figure 15. ovp latched lgate fb osc lgate osc fb
l6730 - L6730B device description 23/52 there is an electrical network between the out put terminal and the fb pin and therefore the voltage at this pin is not a perfec t replica of the output voltage. if the converter can sink current, in the most of cases the low-si de will be turned on before the output voltage exceeds the over- voltage threshold because the error amplifie r will throw off balance in advance. even if the device does not report an overvolt age event, the behavior is the same because the low-side is turned on i mmediately. instead, if the sink mo de is disabled, the low-side will be turned on only when the overvoltage protecti on (ovp) operates and not before because the current can not be reversed. in this case, a delay between the output voltage rising and fb voltage rising can appear and the ovp can turn on late. figure 16. and figure 17. show an overvoltage event in the cases of the sink being enabled or disabled. the output voltage rises with a slope of 100mv s, emulating the breaking of the hi gh-side mosfet as an overvoltage occurs. figure 16. ovp with sink enabled: the low-side mosfet is turned-on in advance. figure 17. ovp with sink disabled: delay on the ovp operation. v out 109% v fb lgate 126% v out v fb lgate
device description l6730 - L6730B 24/52 the L6730B can always sink cu rrent and so the ovp will oper ate always in advance. the device realizes the over-current-protection (ocp) sensing the current both on the high-side mosfet(s) and the low-side mosfet(s) and so 2 current limit thresholds can be set (see och pin and ocl pin in table 3: pins connection ): peak current limit valley current limit the peak current protection is active when the high-side mosfet(s) is turned on, after an adjustable masking time (see chapter 5.10 on page 27 ). the valley-current-protection is enabled when the low-side mosfet(s) is turned on after a fix masking time of about 400ns. if, when the soft-start phase is completed, an over current event occurs during the on time (peak- current-protection) or during the off time (valley-current-protection) the device enters in hiccup mode (l6730): the high-side and low-side mosfet(s) are turned off, the soft-start capacitor is discharged with a constant curren t of 10a and when the voltage at the ss pin reaches 0.5v the soft-start phase restarts. du ring the soft-start phase the ocp provides a constant-current-protection. if during the t on the och comparator triggers an over current the high-side mosfet(s) is immediately turned-off (after the masking time and the internal delay) and returned-on at the next pwm cycle. the limit of this protection is that the ton can?t be less than masking time plus propagation delay (see chapter 5.9: adjustable masking time on page 26 ) because during the masking time the peak-cu rrent-protection is disabled. in case of very hard short circuit, even with this short t on , the current could esca late. the va lley-current- protection is very helpful in this case to limit the current. if during the off-time the ocl comparator triggers an over current, the high-s ide mosfet(s) is not turned-on until the current is over the valley-current- limit. this implies that, if it is necessary, some pulses of the high-side mosfet(s) will be skipped, guaranteeing a maxi mum current due to the following formula: in constant current protection a current control loop limits the value of the error amplifier?s output (comp), in order to avoid its saturation and thus recover faster when the output returns in regulation. figure 18. shows the behaviour of the device during an over current condition that persists also in the soft-start phase. figure 18. constant current and hiccup mode during an ocp (l6730). min on valley max t l vout vin i i , ? ? + = (4) vss vcomp i l
l6730 - L6730B device description 25/52 using the L6730B there is the possibility to set the constant-current-pro tection also after the soft-start. the following figures show the behav iour of the L6730B during an overcurrent event. figure 19. shows the intervention of the peak ocp: the high-side mosfet(s) is turned-off when the current exceeds the ocp threshold. in this way the duty-cycle is reduced, the v out is reduced and so the maximum current can be fixe d even if the output current is escalating. figure 20. shows the limit of this protection: the on-time can be reduced only to the masking time and, if the output current continues to in crease, the maximum current can increase too. notice how the vout remains constant even if the output current increases because the on-time cannot be reduced anymore. figure 19. peak overcurrent-protection in constant-current-protection (L6730B). figure 20. peak ocp in case of heavy overcurrent (L6730B). v out t on i out i l peak th v out i l i out
device description l6730 - L6730B 26/52 if the current is higher than the valley ocp threshold during the off-time, the high-side mosfet(s) will not be turned on. in this way the maximum current can be limited ( figure 21. ). during the constant-current-protection if the vout becomes lower than 80% of the programmed value an uv (under-voltage) is detected and the device enters in hiccup mode. the under- voltage-lock-out (uvlo) is adjust able by the multifunction pin (see chapter 5.10 on page 27 ). it?s possible to set two different thresholds: 4.2v for 5v bus 8.6v for 12v bus working with a 12v bus, setting the uvlo at 8.6v can be very helpful to limit the input current in case of bus fall. 5.9 adjustable masking time by connecting the masking time pin to v ccdr or gnd it is possible to select two different values for the peak current protection leading edge blanking time. this is useful to avoid any false ocp trigger due to spikes and oscilla tions generated at the turn-on of the high-side mosfet(s). the amount of this noise depends very much on the layout, mosfets, free-wheeling diode, switched current, a nd input voltage. when good layout and medium current are used, the minimum masking time can be chosen, while in case of higher noise, it is better to select the maximum masking time. by connecting the t mask pin to v ccdr the masking time is about 400ns, wh ile connecting it to gnd results in about 260ns masking time. figure 21. valley ocp (L6730B). v out i l t off t off valley th
l6730 - L6730B device description 27/52 5.10 multifunction pin (s/o/u l6730) (cc/o/u L6730B) with this pin it is possible: to enable disable the sink mode current capability (l6730) or the constant current protection (L6730B) at the end of the soft-start. to enable or disable the latch-mode for the ovp. to set the uvlo threshold for 5v bus and 12v busses. ta b l e 6 shows how to set the different options through an external resistor divider: figure 22. external resistor table 6. s/o/u and cc/o/u pin r1 r2 v sou /v ccdr uvlo ovp sink cc n.c 0 ? 0 5v bus not latched not 11k ? 2.7k ? 0.2 5v bus not latched yes 6.2k ? 2.7k ? 0.3 5v bus latched not 4.3k ? 2.7k ? 0.4 5v bus latched yes 2.7k ? 2.7k ? 0.5 12v bus not latched not 1.8k ? 2.7k ? 0.6 12v bus not latched yes 1.2k ? 2.7k ? 0.7 12v bus latched not 0 ? n.c 1 12v bus latched yes r1 r2 l6730 / b s/o/u cc/o/u vccdr
device description l6730 - L6730B 28/52 5.11 synchronization the presence of many converters on the same board can generate beating frequency noise. to avoid this it is important to make them operate at the same switching frequency. moreover, a phase shift between different modules helps to minimize the rms current on the common input capacitors. figure 23. shows the results of two modules in synchronization. two or more devices can be synchronized simply connecting together the synch pins. the device with the higher switching frequency will be the master while the other one will be the slave. the slave controller will increase its switch ing frequency reducing the ramp amplitude proportionally and then the modulator ga in will be increased. to avoid a huge variation of the modulator gain, the best way to synchronize two or more devices is to make them work at the same switching frequency and, in any case, the switching frequencies can differ for a maximum of 50% of the lowest one. if, during synchronization between two (or more) l6730, it?s important to know in advance which the master is, it?s timely to set its switching frequency at least 15% higher than the slave. using an external clock signal (f ext ) to synchronize one or more devices that are working at a different switching frequency (f sw ) it is recommended to follow the below formula: the phase shift between master and slaves is approximately done 180. 5.12 thermal shutdown when the junction temperature reaches 150c 10 c, the device enters in thermal shutdown. both mosfets are turned off and the soft-s tart capacitor is rapidly discharged with an internal switch. the device does not restart until the junction temperature goes down to 120c and, in any case, until the voltage at the soft-start pin reaches 500mv. figure 23. synchronization. sw ext sw f f f ? 3 , 1 pwm signals inductor currents
l6730 - L6730B device description 29/52 5.13 minimum on-time t on(min) the device can manage minimum on times lowe r than 100ns. this feature comes from the control topology as well as fr om the particular l6730/b over current protection system. in a voltage mode controller, the current does not have to be sensed to perform regulation and, in the case of l6730/b, it does not have to be sensed for the overcurrent protection either because valley current protection can operate during the off time. the first advantage related of this feature is the achievement of extremely low conversion ratios. figure 24. shows a conversion from 14v to 0.5v at 820khz with a t on of about 50ns. the on time is limited by the mosfet turn-on and turn-off times. figure 24. 14v -> 0.5v@820khz, 5a 50ns
device description l6730 - L6730B 30/52 5.14 bootstrap anti-discharging system this built-in anti-discharging system keeps th e voltage going across the bootstrap capacitor from going below 3.3v. an internal comparator senses the voltage across the external bootstrap capacitor and helps to keep it charged, eventually turning on the low-side mosfet for approximately 200ns. if the bootstrap capacitor is not charged up enough, the high-side mosfet cannot be effectively turned on and it will pres ent a higher r ds(on) . in some cases, the ocp can be also triggered. there are up to two conditions during which the bootstrap capacitor can be discharged: fan power supply failure, and no sink at zero current operation. 5.14.1 fan power supply failure in many applications the fan is driven by a dc motor that uses a dc/dc converter. often only the speed of the motor is controlled by varying the voltage applied to the input terminal and there is no control on the torque because the current is not directly controlled. the current has to be limited in case of overload or short-circuit, but without stopping the motor. with the L6730B, the current can be limited without shutting down the system because constant current protection is provided. in order to vary the motor speed, the output voltage of the converter must be varied. both l6730 and L6730B have a dedicated earef pin (see ta b l e 3. ) which provides an external reference to the non-inverting input of the error-amplifier. in these applications the duty cycle depends on the motor?s speed and sometimes a 100% duty cycle setting has to be used to attain the maxi mum speed. in these c onditions, the bootstrap capacitor can not be recharged and the system cannot work properly. some pwm controllers limit the maximum duty cycle to 80 or 90% in order to keep the bootstrap capacitor charged, but this makes performance during the load transient worse. the ?bootstrap anti-discharging system? allows the l6730x to work at 100% without any problem. figure 25.: 100% duty cycle operation on page 31 shows the following picture illustrates the device behavior when the input voltage is 5v and a 100% duty cycle is set by an external reference.
l6730 - L6730B device description 31/52 figure 25. 100% duty cycle operation vout=5v vin=5v lgate fsw?6.3khz toff 200ns
device description l6730 - L6730B 32/52 5.14.2 no-sink at zero current operation the l6730 can work in no-sink mode. if output current is zero the converter skip some pulses and works with a lower switching frequency. between two pulses can pass a relatively long time (say 200-300s) during which there?s no switching activity and the current into the inductor is zero. in this condition the phase node is at the output voltage and in some cases this is not enough to keep the bootstrap cap charged. for ex ample, if vout is 3.3v the voltage across the bootstrap cap is only 1.7v. the high-side mosf et cannot be effectively turned-on and the regulation can be lost. thanks to the ?bootstrap anti-discharging system? the bootstrap cap is always kept charged. the following picture show s the behaviour of the device in the following conditions: 12v ? 3.3v@0a. it can be observed that between tw o pulses trains the low-side is turned-on in order to keep the bootstrap cap charged. figure 26. 12v -> 3.3v@0a in no-sink pulse train minimum bootstrap voltage v phase v boot i l
l6730 - L6730B application details 33/52 6 application details 6.1 inductor design the inductance value is defined by a compromi se between the transient response time, the efficiency, the cost and the size. the inductor has to be calculated to maintain the ripple current ( ? i l ) between 20% and 30% of the maximum outp ut current. the inductance value can be calculated with the following relationship: where f sw is the switching frequency, v in is the input voltage and v out is the output voltage. figure 27. shows the ripple current vs. the output voltage for different values of the inductor, with v in = 5v and v in = 12v at a switching frequency of 400khz. increasing the value of the inductance reduces the current ripple but, at the same time, increases the converter response time to a load transient. if the compensation network is well designed, during a load transient the device is able to set the duty cycle to 100% or to 0%. when one of these conditions is reached, the re sponse time is limited by the time required to change the inductor current. during this time the output current is supplied by the output capacitors. minimizing the response time can minimize the output capacitor size. figure 27. inductor current ripple. vin vout i fsw vout vin l l ? ? ? ? ? (6) 0 1 2 3 4 5 6 7 8 01234 output voltage (v) inductor current rippl v in = 5 v , l=500nh v in = 5 v , l = 1 .5 u h v in = 1 2 v , l = 2 u h v in = 1 2 v , l = 1 u h
application details l6730 - L6730B 34/52 6.2 output capacitors the output capacitors are basic components for the fast transient response of the power supply. they depend on the output voltage ripple requirements, as well as any output voltage deviation requirement during a load transient. during a load transient, the output capacitors supply the current to the load or absorb the curr ent stored into the inductor until the converter reacts. in fact, even if the controller recognizes immediately the load transient and sets the duty cycle at 100% or 0%, the current slope is limited by the inductor value. the output voltage has a first drop due to the current variation inside t he capacitor (neglecting the effect of the esl): moreover, there is an additional drop due to the effective capacitor discharge or charge that is given by the following formulas: formula (8) is valid in case of positive load transient while the formula (9) is valid in case of negative load transient. d max is the maximum duty cycle value that in the l6730/b is 100%. for a given inductor value, minimum input voltage, output voltage and maximum load transient, a maximum esr, and a minimum c out value can be set. the esr and c out values also affect the static output voltage ripple. in the worst ca se the output voltage ripple can be calculated with the following formula: usually the voltage drop due to the esr is the biggest one while the drop due to the capacitor discharge is almost negligible. 6.3 input capacitors the input capacitors have to sustain the rms current flowing through them, that is: where d is the duty cycle. the equation reaches its maximum value, i out /2 with d = 0.5. the losses in worst case are: esr iout vout esr ? ? = ? (7) ) max min , ( 2 2 vout d vin cout l iout vout cout ? ? ? ? ? ? = ? (8) vout cout l iout vout cout ? ? ? ? = ? 2 2 (9) ) 8 1 ( fsw cout esr i vout l ? ? + ? ? = ? (10) ) 1 ( d d iout irms ? ? ? = (11) 2 ) 5 . 0 ( iout esr p ? ? = (12)
l6730 - L6730B application details 35/52 6.4 compensation network the loop is based on a voltage mode control ( figure 28. ). the output voltage is regulated to the internal/external reference voltage and scaled by the external resistor divider. the error amplifier output v comp is then compared with the oscillator triangular wave to provide a pulse- width modulated (pwm) with an amplitude of v in at the phase node. this waveform is filtered by the output filter. the modulator transfer func tion is the small signal transfer function of v out / v comp . this function has a double pole at frequency f lc depending on the l-cout resonance and a zero at f esr depending on the output capacitor?s esr. the dc gain of the modulator is simply the input voltage v in divided by the peak-to-pe ak oscillator voltage: v osc . the compensation network consists in the internal error amplifier, the impedance networks z in (r3, r4 and c20) and z fb (r5, c18 and c19). the compensation network has to provide a closed loop transfer function with the highest 0db crossing frequency to have fastest transient response (but always lower than fsw/10) and the highest gain in dc conditions to minimize the load regulation error. a stable control loop ha s a gain crossing the 0db axis with -20db/decade slope and a phase margin greater than 45. to locate poles and zeroes of the compensation networks, the following suggestions may be used: modulator singularity frequencies: compensation network singularity frequencies: figure 28. compensation network z fb z in cout l lc ? = 1 (13) cout esr esr ? = 1 (14) ? ? ? ? ? ? ? ? + ? ? = 19 18 19 18 5 1 1 c c c c r p (15) 20 4 2 1 c r p ? = (16) 19 5 1 1 c r z ? = (17) () 4 3 20 2 1 r r c z + ? = (18)
application details l6730 - L6730B 36/52 compensation network design: ? put the gain r 5 /r 3 in order to obtain the desired converter bandwidth ? place z1 before the output filter resonance lc ; ? place z2 at the output filter resonance lc ; ? place p1 at the output capacitor esr zero esr ; ? place p2 at one half of the switching frequency; ? check the loop gain considering the error amplifier open loop gain. 6.5 two quadrant or one quadrant operation mode (l6730) after the soft-start phase the l6730 can work in source only (one quadrant operation mode) or in sink/source (two quadrant operation mode), depending on the setting of the multifunction pin (see chapter 5.10 on page 27 ). the choice of one or two quadrant operation mode is related to the application. one quadrant operation mode permits to have a higher efficiency at light load, because the converter works in discontinuous mode (see figure 30. ). nevertheless in some cases, in order to maintain a constant switching frequency, it?s preferable to work in two quadrants, even at light load. in this way the reduction of the switching frequency due to the pulse skipping is avoided. to parallel two or more modules is requested the one quadrant operation in order not to have current sinking between different converters. finally the two quadrant operation allows faster recovers after negative load transient. for example, let?s consider that the load current falls down from i out to 0a with a slew rate sufficiently greater than l/v out (where l is the inductor value). even considering that the converter reacts instantaneously setting to 0% the duty-cycle, the energy ?*l*i out 2 stored in the inductor will be transferred to the output capacitors, increasing the output voltage. if the converter can sink current this overvoltage can be faster eliminated. figure 29. asymptotic bode plot of converter's open loop gain lc c vosc vin r r ? ? ? ? ? = 3 5 (18)
l6730 - L6730B application details 37/52 figure 30. efficiency in discontinuous-current-mode and continuous-current-mode. efficiency: dcm vs. ccm 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 output current (a) eff. (% efficiency dcm efficiency ccm
l6730 demo board l6730 - L6730B 38/52 7 l6730 demo board 7.1 description l6730 demo board realizes in a four layer pcb a step-down dc/dc converter and shows the operation of the device in a general purpose app lication. the input voltage can range from 4.5v to 14v and the output voltage is at 3.3v. the mo dule can deliver an output current in excess of 30a. the switching frequency is set at 400 khz (controller free-running f sw ) but it can be increased up to 1mhz. a 7 positions dip-switch a llows to select the uvlo threshold (5v or 12v bus), the ovp interven tion mode and the sink-m ode current capability. figure 31. demo board picture. top side bottom side
l6730 - L6730B l6730 demo board 39/52 7.2 pcb layout figure 32. top layer figure 33. power ground layer figure 34. signal ground layer figure 35. bottom layer
l6730 demo board l6730 - L6730B 40/52 figure 36. demo board schematic table 7. demoboard part list reference value manufacturer package supplier r1 820 ? neohm smd 0603 ifarcad r2 0 ? neohm smd 0603 ifarcad r3 n.c. r4 10 ? 1% 100mw neohm smd 0603 ifarcad r5 11k 1% 100mw neohm smd 0603 ifarcad r6 6k2 1% 100mw neohm smd 0603 ifarcad r7 4k3 1% 100mw neohm smd 0603 ifarcad r8 2k7 1% 100mw neohm smd 0603 ifarcad r9 1k8 1% 100mw neohm smd 0603 ifarcad r10 1k2 1% 100mw neohm smd 0603 ifarcad r11 2k7 1% 100mw neohm smd 0603 ifarcad r12 1k neohm smd 0603 ifarcad
l6730 - L6730B l6730 demo board 41/52 r13 2k7 1% 100mw neohm smd 0603 ifarcad r14 1k 1% 100mw neohm smd 0603 ifarcad r15 1k 1% 100mw neohm smd 0603 ifarcad r16 4k7 1% 100mw neohm smd 0603 ifarcad r17 n.c. r18 2.2 ? neohm smd 0603 ifarcad r19 2.2 ? neohm smd 0603 ifarcad r20 10k 1% 100mw neohm smd 0603 ifarcad r21 n.c. r22 n.c. r23 0 ? neohm smd 0603 ifarcad c1 220nf kemet smd 0603 ifarcad c3-c7-c9-c15-c21 100nf kemet smd 0603 ifarcad c2 1nf. kemet smd 0603 ifarcad c4-c6 100uf 20v oscon 20sa100m radial 10x10.5 sanyo c8 4.7uf 20v avx sma6032 ifarcad c10 10nf kemet smd 0603 ifarcad c11 n.c. c12 47nf kemet smd 0603 ifarcad c13 1.5nf kemet smd 0603 ifarcad c14 4.7nf kemet smd 0603 ifarcad c18-c19 330uf 6.3v poscap 6tpb330m smd sanyo c20 n.c. l1 1.8uh panasonic smd st d1 1n4148 st sot23 ifarcad d2 sts1l30m st do216aa st q1-q2 sts12nh3ll st so8 st q4-q5 stsj100nh3ll st so8 st u1 l6730 st htssop20 st switch dip switch 7 pos. st table 7. demoboard part list
l6730 demo board l6730 - L6730B 42/52 table 8. other inductor manufacturer manufacturer series inductor va lue (h) saturation current (a) wurth elektronic 744318180 1.8 20 sumida cdep134-2r7mc-h 2.7 15 epcos hpi_13 t640 1.4 22 tdk spm12550t-1r0m220 1 22 toko fda1254 2.2 14 coiltronics hcf1305-1r0 1.15 22 hc5-1r0 1.3 27 table 9. other capacitor manufacturer manufacturer series capacitor value(f) rated voltage (v) tdk c4532x5r1e156m 15 25 c3225x5r0j107m 100 6.3 nippon chemi-con 25ps100mj12 100 25 panasonic ecj4yb0j107m 100 6.3
l6730 - L6730B i/o description 43/52 8 i/o description figure 37. demoboard table 10. i/o functions symbol function input (vin-gin) the input voltage can range from 1.8v to 14v. if the input voltage is between 4.5v and 14v it can supply also the device (through the v cc pin) and in this case the pin 1 and 2 of the jumper g1 must be connected together. output (v out -g out ) the output voltage is fixed at 3.3v but it can be changed by replacing the resistor r14 of the output resistor divider: the over-current-protection limit is set at 15a but it can be changed by replacing the resistors r1 and r12 (see ocl and och pin in table 3: pins connection ). v cc -gnd cc using the input voltage to supply the controller no power is required at this input. however the controller can be supplied separately from the power stage through the v cc input (4.5-14v) and, in this case, jumper g1 must be left open. v ccdr an internal ldo provides the power into the device. the input of this stage is the v cc pin and the output (5v) is the v ccdr pin. the ldo can be bypassed, providing directly a 5v voltage from v ccdr and gndcc. in this case the pins 1 and 3 of the jumper g1 must be shorted. tp1 this pin can be used as an input or as a test po int. if all the jumper g2 pins are shorted, tp1 can be used as a test point of the voltage at the earef pin. if the pins 2 and 3 of g2 are connected together, tp1 can be used as an input to provide an external reference for the internal error amplifier (see section 4.3. internal and external references). tp2 this test point is connected to the tmask pin (see table 3: pins connection ). tp3 this test point is connected to the s/o/u pin (see chapter 5.10 on page 27 ). ) 1 ( 14 16 r r v vo ref + ? =
i/o description l6730 - L6730B 44/52 synch this pin is connected to the synch pin of the controller (see chapter 5.11 on page 28 ). pwrgd this pin is connected to the pgood pin of the controller. dip switch different positions of the dip s witch correspond to different sett ings of the multifunction pin (s/o/u) (cc/o/u). table 11. dip switch uvlo ovp sink cc vsou/v ccdr dip switch state 5v not latched not 0 s7 a 5v not latched yes 0.2 s1-s7 b 5v latched not 0.3 s2-s7 c 5v latched yes 0.4 s3-s7 d 12v not latched not 0.5 s4-s7 e 12v not latched yes 0.6 s5-s7 f 12v latched not 0.7 s6-s7 g 12v latched yes 1 s1 h table 10. i/o functions
l6730 - L6730B efficiency 45/52 9 efficiency the following figures show the demo board efficiency versus load current for different values of input voltage and switching frequency: figure 38. demoboard efficiency 400khz figure 39. demoboard efficiency 645khz fsw=400khz 75.00% 80.00% 85.00% 90.00% 95.00% 13579111315 iout (a) efficienc y v in = 5v v in = 12v v o = 3.3v v in = 5v v in = 5v fsw=645khz 70.00% 75.00% 80.00% 85.00% 90.00% 95.00% 13579111315 iout (a) efficienc y v in = 12v v in = 5v v o = 3.3v
efficiency l6730 - L6730B 46/52 figure 40. demoboard efficiency 1mhz figure 41. efficiency with 2xsts12nh3ll+2xstsj100nh3ll fsw=1mhz 60.00% 65.00% 70.00% 75.00% 80.00% 85.00% 90.00% 95.00% 13579111315 iout (a) efficienc y v in = 12v v in = 5v v o = 3.3v 12v-->3.3v 0.87 0.88 0.89 0.9 0.91 0.92 0.93 0.94 0.95 0.96 3 5 7 9 11 13 15 17 19 output current (a) efficiency (%) 400khz 700khz 1mhz
l6730 - L6730B pol demoboard 47/52 10 pol demoboard 10.1 description a compact demoboard has been designed to manage currents in the range of 10-15a. figure 38. shows the schematic and table 9. the part list. multi-layer- ceramic-capacitors (mlccs) have been used on the input and the output in order to reduce the overall size. figure 42. pol demoboard schematic. table 12. pol demoboard part list. reference value manufacturer package supplier r1 1k8 ? neohm smd 0603 ifarcad r2 10k ? neohm smd 0603 ifarcad r3 n.c. r4 10 ? neohm smd 0603 ifarcad r5 11k 1% 100mw neohm smd 0603 ifarcad r6 2k7 1% 100mw neohm smd 0603 ifarcad r7 n.c. neohm smd 0603 ifarcad r8 0 ? neohm smd 0603 ifarcad r9 3k 1% 100mw neohm smd 0603 ifarcad r10 4k7 1% 100mw neohm smd 0603 ifarcad
pol demoboard l6730 - L6730B 48/52 r11 15 ? 1% 100mw neohm smd 0603 ifarcad r12 4k7 1% 100mw neohm smd 0603 ifarcad r13 1k 1% 100mw neohm smd 0603 ifarcad r14 2.2 ? neohm smd 0603 ifarcad r15 2.2 ? neohm smd 0603 ifarcad c1-c7 220nf kemet smd 0603 ifarcad c6- c19-c20-c9 100nf kemet smd 0603 ifarcad c2 1nf kemet smd 0603 ifarcad c11 n.c. c12 68nf kemet smd 0603 ifarcad c13 220pf kemet smd0603 ifarcad c8 4.7uf 20v avx sma6032 ifarcad c14 6.8nf kemet smd 0603 ifarcad c3-c4-c5 15uf tdk mlc c4532x5r1e156m smd1812 ifarcad c15-c16-c17-c18 100uf panasonic mlc p/n ecj4yboj107m smd 1210 ifarcad l1 1.8uh panasonic smd st d1 sts1l30m st do216aa st q1 sts12nh3ll st power so8 st q2 stsj100nh3ll st power so8 st u1 l6730 st htssop20 st figure 43. pol demoboard efficiency table 12. pol demoboard part list. 12v-->3.3v@400khz 0.82 0.84 0.86 0.88 0.9 0.92 0.94 1357911 output current (a) efficienc y
l6730 - L6730B package mechanical data 49/52 11 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect . the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com.
package mechanical data l6730 - L6730B 50/52 table 13. htssop20 mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.200 0.047 a1 0.150 0.006 a2 0.800 1.000 1.050 0.031 0.039 0.041 b 0.190 0.300 0.007 0.012 c 0.090 0.200 0.003 0.008 d (1) 1. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 6.400 6.500 6.600 0.252 0.256 0.260 d1 (3) 2.200 0.087 e 6.200 6.400 6.600 0.244 0.252 0.260 e1 (2) 2. dimension ?e1? does not include interl ead flash or protrusions. intelead flash or protrusions shall not exceed 0.25mm per side. 4.300 4.400 4.500 0.170 0.173 0.177 e2 (3) 3. the size of exposed pad is variable depending of leadframe design pad size. end user s hould verify ?d1? and ?e2? dimensions for eac h device application. 1.500 0.059 e 0.650 0.025 l 0.450 0.600 0.750 0.018 0.024 0.030 l1 1.000 0.039 k 0 min., 8 max. aaa 0.100 0.004 figure 44. package dimensions
l6730 - L6730B revision history 51/52 12 revision history date revision changes 21-dec-2005 1 in itial release. 29-may-2006 2 new template, thermal data updated
l6730 - L6730B 52/52 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorize representative of st, st products are not designed, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems, where failure or malfunction may result in personal injury, death, or severe property or environmental damage. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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